The present invention relates to memory redundancy architectures, and in particular, to an architecture for burst interleaved memories.
Redundancy is a hardware technique that allows the recovering of eventual defects of a memory array to increase the effective yield of the fabrication process of the device. In most cases, when speaking of redundancy a xe2x80x9ccolumnxe2x80x9d redundancy is generally intended. Matrix columns containing one or more defects are substituted with spare or redundant columns.
The commonly used architecture for managing the addresses of redundant locations is mainly formed by banks of non-volatile memory units, which are referred to as CAM herein. Each CAM can be programmed and erased by the manufacturer during a phase of testing of the devices. These CAMs store information suitable to identify the memory location to be substituted.
Different kinds of information can be stored in a CAM. Information includes addresses of the location to be repaired, which packet of bit of an addressed word must be replaced, whether or not the bank of the CAM is used to store a failed address, etc.
The function of a redundancy managing architecture is to verify whether or not the failed addressed location is among the redundant ones, and in case of a positive result, to activate the redundant columns and at the same time to deactivate the decoding of the defective location of the matrix. This must be done for any operation, reading or writing, that implies addressing the defective or failed location.
The number of CAMs used in a redundancy architecture sets the maximum number of packets (columns, byte, rows . . . ) of the whole array of memory cells that can be redundant or substituted. In a traditional functioning of a standard (asynchronous) memory, there are no particular difficulties in dedicating a redundancy packet to any failed column of the memory, nor are there any restrictions on activation times of any redundant element. In contrast, in the case of synchronous memories operating with a burst interleaved protocol, there is the need of properly differentiating the activation instants for contiguous redundant locations during burst read cycles.
In fact, in a burst interleaved access mode, two contiguous readings (e.g., add0xe2x86x92add1) are carried out with a certain time overlap. This means that, while data is being output, the successive data has been already addressed and is in the process of being read. Therefore, it is clear that redundancy architectures for this kind of interleaved memories must consider this peculiarity in order to differentiate correctly without conflicts, the turn-on instant of the redundancy elements. For example, two contiguous locations that are both redundant may be addressed according to a burst access mode.
Normally the redundancy architecture is similar to the corresponding decoding structure of the memory matrix. Similarly, by referring to the architecture of a typical matrix, the redundancy unit is formed, as depicted in FIG. 1, by a main bit line (MBL) (defined in Metal2), starting from which, four real bit lines (defined in Metal1) that are connected to the drains of the respective redundancy cells, are decoded.
To form a column redundancy, two alternative approaches are normally followed. A first approach is redundancy at the output, i.e., replacement of the single line to which the fail belongs. A second approach is redundancy by packets, which is a full or partial substitution of the group of bit lines of the word affected by a fail, as addressed during a reading.
For example, the redundancy architecture may contemplate the repairing of an 8-bit packet (i.e., of the byte high or of the byte low) of an addressed 16-bit word, irrespectively of the fact that the defect can be verified on a single bit of one of the bytes and not on all the 8-bits.
According to this second approach, there is a waste of area due to the superfluous number of columns that in the majority of repairings of single bit failures would not be necessary. On the other hand, a greatly simplified circuitry for managing the redundancy is required. This reduces the silicon area of integration of the managing circuitry. For example, there may be four redundancy banks for the whole array, i.e., the possibility of using four column packets for eventual replacements.
In an interleaved memory, the whole array of cells is split in several parts (typically in two semi-arrays EVEN/ODD) that are singularly addressable to avoid problems in managing two partly time overlapped readings as previously discussed. The number of sense amplifiers are equal to the number of outputs.
In a classical memory, the selection of the redundant column and the deselection of the column to be redundant is commonly done by acting on the first decoding level while the other decoding levels of the memory matrix remain active. On the contrary, the last decoding level that determines which of the bit lines connect to the MBL itself (FIG. 1) will be the selected one, and is active for both the memory matrix and the redundancy structure.
Normally, the read bus is common to both the memory matrix and the redundancy structure. So when a repaired location is addressed, the matrix local decoding is disabled while the redundancy local decoding is activated. This allows the connection between the redundant physical column and the sensing circuitry.
By implementing a redundancy per byte, only the matrix local decoding of the word to which the packet (byte) to be replaced belongs will be deactivated, while the other eight local decodings will still be selecting a matrix location. It is clear that the redundancy, which is essential to guarantee an acceptable yield of the fabrication process, has a cost in terms of silicon area consumption, and therefore, it is of great importance to optimize its performances while minimizing the area dedicated to it.
It has been found that great advantages can be attained by subdividing the number of redundancy column packets in subgroups, each one addressable independently from the other subgroups and providing columns of redundancy cells only for a respective bank in which the memory cell array is divided. Each subgroup of packets of redundancy columns has a capacity appropriate to satisfy statistically determined needs of possible bit failure of the single bank to which the subgroup is associated.
The redundancy selection circuitry, or the number of banks of CAMs, remains unchanged because nothing else is modified. In practice, the total number of packets of redundancy columns is simply split, i.e., subdivided into subgroups. This arrangement proves itself extremely advantageous. It simplifies the managing of the redundancy and determines a saving of silicon area.
In particular, the approach of the invention does not impose any restriction despite the fact that it is no longer possible to substitute (redundant) two bytes of a same addressed location (word). On the other hand, the condition of independence of redundancy for the banks of subdivision of an interleaved memory is fully accomplished allowing, as already discussed above, the possibility of having redundant successive locations that could be read during the same time interval when accessing the memory in burst mode.
Another advantage of the subdivision of the redundancy architectures in distinct subgroups includes the fact that in terms of layout, the amplitude of the read and write buses for a memory organized in 16-bit words can be 16 bits only along the whole width of the physical memory array because the buses to which the redundant MBL will be eventually connected will be local and related to a single bank (in the case of an interleaved memory) and to a single read/write path.
For the same design choice of redundancy by bytes, a commonly used technique to save area includes using separately the four right columns and the four left columns of a packet of eight columns, thus dividing in two portions a full packet of redundancy columns.
However, this known technique has the following drawbacks. It is impossible to have two successive redundant locations according to the burst-interleaved reading mode, because it is not possible to activate at the same time 16 main bit lines related to two redundant bytes of the two successive locations (EVEN-ODD) during the same reading cycle. Another drawback is the difficulty in routing the read/write bus that must have a 32-bit width for the whole width of the array of memory cells, because redundancy of all the banks using the same elements (spare packets of columns) must be ensured.
According to another aspect of the invention, a number of banks of non-volatile registers (CAM) equal to the maximum number of substitutions that must be ensured, defined during the design of the device, associate to each bank of subdivision of the cells of the whole memory array (typically two semi-arrays of an interleaved memory) a number of redundancy packets. This number is equal to a pre-defined number of banks of non-volatile registers (CAM).
For each of the two address systems relative to the subdivision banks of the memory array, for example, relative to the EVEN semi-array and to the ODD semi-array of an interleaved memory, suitable XOR structures and one or more non-volatile registers are used for selecting the semi-array affected by defects. One or more structures of non-volatile registers thus selecting the portion of an addressed word must be substituted.
This approach allows a reduction (a halving, in the case of a two bank interleaved memory) of the required number of non-volatile registers with a consequent silicon area saving. Moreover, this architecture for managing the redundancy has great flexibility. In fact, the redundancy resources can be freely assigned to any subdivided bank of the array and in any combination and/or ratio.
Essentially, according to the present invention, a double XOR structure for generating the HIT signals and a CAM dedicated to the storage of the most significant column address used as a multiplexing signal of the HIT signal towards the correct portion of the array, for example, towards the EVEN bank or towards the ODD bank of a common interleaved memory subdivided in two semi-arrays, are used.